View MAX1875-MAX1876_1595767.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max1875/max1876 dual, synchronized, step-down controller generates two outputs from input supplies ranging from 4.75v to 23v. each output is adjustable from sub-1v to 18v and supports loads of 10a or higher. input voltage ripple and total rms input ripple current are reduced by synchronized 180 out-of-phase operation. the switching frequency is adjustable from 100khz to 600khz with an external resistor. alternatively, the con- troller can be synchronized to an external clock gener- ated to another max1875/max1876 or a system clock. one max1875/max1876 can be set to generate an in- phase, or 90 out-of-phase, clock signal for synchro- nization with additional controllers. this allows two controllers to operate either as an interleaved two- or four-phase system with each output shifted by 90? these devices also feature soft-start and soft-stop. the max1875/max1876 eliminate the need for current- sense resistors by utilizing the low-side mosfet? on- resistance as a current-sense element. this protects the dc-dc components from damage during output- overload conditions or when output short-circuit faults without requiring a current-sense resistor. adjustable foldback current limit reduces power dissipation during short-circuit conditions. the max1876 includes a power-on reset output to signal the system when both outputs reach regulation. the max1875/max1876 are available in a 24-pin qsop package. an evaluation kit is available to speed designs. applications network power supplies telecom power supplies dsp, asic, and fpga power supplies set-top boxes broadband routers servers features two independent output voltages 180 out-of-phase operation 90 out-of-phase operation (using two max1875/max1876s) foldback current limit 4.75v to 23v input supply range 0 to 18v output-voltage range (up to 10a) >90% efficiency fixed-frequency pulse-width modulation (pwm) operation adjustable 100khz to 600khz switching frequency external sync input clock output for master/slave synchronization soft-start and soft-stop rst output with 140ms minimum delay (max1876) lossless current limit (no sense resistor) max1875/max1876 dual 180 out-of-phase pwm step- down controllers with por ________________________________________________________________ maxim integrated products 1 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 en lx2 dh2 bst2 osc ilim2 fb2 comp2 top view dl2 v l pgnd dl1 cko gnd ref v+ 16 15 14 13 9 10 11 12 bst1 dh1 lx1 comp1 fb1 ilim1 sync qsop max1875/ max1876 rst (max1876 only) pin configuration ordering information 19-2431; rev 0; 7/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max1875 eeg -40 c to +85 c 24 qsop max1876 eeg -40 c to +85 c 24 qsop typical operating circuit appears at end of data sheet.
max1875/max1876 dual 180 out-of-phase pwm step- down controllers with por 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd ..............................................................-0.3v to +25v pgnd to gnd .......................................................-0.3v to +0.3v v l to gnd ..................-0.3v to the lower of +6v and (v+ + 0.3v) bst1, bst2 to gnd ...............................................-0.3v to +30v lx1 to bst1..............................................................-6v to +0.3v lx2 to bst2..............................................................-6v to +0.3v dh1 to lx1 ..............................................-0.3v to (v bst1 + 0.3v) dh2 to lx2 ..............................................-0.3v to (v bst2 + 0.3v) dl1, dl2 to pgnd........................................-0.3v to (v l + 0.3v) cko, ref, osc, ilim1, ilim2, comp1, comp2 to gnd ..........................-0.3v to (v l + 0.3v) fb1, fb2, rst , sync, en to gnd...........................-0.3v to +6v vl to gnd short circuit .............................................continuous ref to gnd short circuit ...........................................continuous continuous power dissipation (t a = +70 c) 24-pin qsop (derate 9.4mw/ c above +70 c)...........762mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (v+ = 12v, en = ilim_ = v l , sync = gnd, i vl = 0ma, pgnd = gnd, c ref = 0.22f, c vl = 4.7f (ceramic), r osc = 60k ? , compensation components for comp_ are from figure 1, t a = -40 c to +85 c (note 1), unless otherwise noted.) parameter conditions min typ max units general (note 2) 4.75 23 v+ operating range v l = v+ (note 2) 4.75 5.5 v v+ operating supply current v l unloaded, no mosfets connected 3.5 6 ma v+ standby supply current en = lx_ = fb_ = 0v r osc = 60k ? 0.3 0.6 ma thermal shutdown rising temperature, typical hysteresis = 10 c 160 c ilim_ = v l 75 100 125 mv r ilim_ = 100k ? 32 50 62 mv current-limit threshold pgnd - lx_ r ilim_ = 600k ? 225 300 375 mv v l regulator output voltage 5.5v < v+ < 23v, 1ma < i load < 50ma 4.75 5 5.25 v v l undervoltage lockout trip level 4.4 4.55 4.7 v reference output voltage i ref = 0a 1.98 2.00 2.02 v reference load regulation 0a < i ref < 50a 0 4 10 mv soft-start digital ramp period internal 6-bit dac for one converter to ramp from 0v to full scale (note 3) 1024 dc-dc clocks soft-start steps 64 steps frequency 0 c to +85 c 84 100 115 low end of range r osc = 60k ? -40 c to +85 c 80 100 120 khz high end of range r osc = 10k ? 540 600 660 khz dh_ minimum off-time r osc = 10k ? 250 303 ns
max1875/max1876 dual 180 out-of-phase pwm step- down controllers with por _______________________________________________________________________________________ 3 electrical characteristics (continued) (v+ = 12v, en = ilim_ = v l , sync = gnd, i vl = 0ma, pgnd = gnd, c ref = 0.22f, c vl = 4.7f (ceramic), r osc = 60k ? , compensation components for comp_ are from figure 1, t a = -40 c to +85 c (note 1), unless otherwise noted.) parameter conditions min typ max units sync range internal oscillator nominal frequency must be set to half of the sync frequency 200 1200 khz high 100 sync input pulse width (note 3) low 100 ns sync rise/fall time (note 3) 100 ns error amplifier fb_ input bias current 250 na 0 c to +85 c 0.985 1.00 1.015 fb_ input voltage set point -40 c to +85 c 0.98 1.00 1.02 v 0 c to +85 c 1.25 1.8 2.70 fb_ to comp_ transconductance -40 c to +85 c 1.2 1.8 2.9 ms drivers dl_, dh_ break-before-make time c load = 5nf 30 ns low 1.5 2.5 dh_ on-resistance high 3 5 ? low 0.6 1.5 dl_ on-resistance high 3 5 ? logic inputs (en, sync) input low level typical 15% hysteresis, v l = 4.75v 0.8 v input high level v l = 5.5v 2.4 v input high/low bias current v en = 0 or 5.5v -1 0.1 +1 a logic outputs (cko) output low level v l = 5v, sinking 5ma 0.4 v output high level v l = 5v, sourcing 5ma 4.0 v comp_ pulldown resistance during shutdown and current limit 17 ? rst output (max1876 only) output-voltage trip level both fbs must be over this to allow the reset timer to start; there is no hysteresis 0.87 0.9 0.93 v v l = 5v, sinking 3.2ma 0.4 output low level v l = 1v, sinking 0.4ma 0.3 v output leakage v+ = v l = 5v, v rst = 5.5v, v fb = 1v 1 a reset timeout period v fb_ = 1v 140 315 560 ms fb_ to reset delay fb_ overdrive from 1v to 0.85v 4 s note 1: specifications to -40 c are guaranteed by design and not production tested. note 2: operating supply range is guaranteed by v l line regulation test. connect v+ to v l for 5v operation. note 3: guaranteed by design and not production tested.
max1875/max1876 dual 180 out-of-phase pwm step- down controllers with por 4 _______________________________________________________________________________________ typical operating characteristics (circuit of figure 1, v in = 12v, t a = +25 c, unless otherwise noted.) efficiency vs. load max1875 toc01 load (a) efficiency (%) 10 1 10 20 30 40 50 60 70 80 90 100 0 0.1 100 out2 out1 output-voltage accuracy vs. load max1875 toc02 load (a) output voltage accuracy (%) 10 5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 015 out2 out1 v l voltage accuracy vs. load current max1875 toc03 load current (ma) v l voltage accuracy 100 50 -1.5 -1.0 -0.5 0 0.5 -2.0 0 150 switching frequency vs. r osc max1875 toc04 r osc (k ? ) switching frequency (khz) 50 40 30 20 10 100 200 300 400 500 600 0 060 load transient response (output 1) max1875 toc05 10 s/div 0a i out1 10a v out1 50mv/div ac-coupled v out2 50mv/div ac-coupled load transient response (output 2) max1875 toc06 10 s/div 0a i out2 10a v out1 50mv/div ac-coupled v out2 50mv/div ac-coupled
soft-start and soft-stop waveform max1875 toc07 1ms/div 0v 1v/div 0v 1v/div v out2 v out2 5v 0v en reset timeout (max1876 only) max1875 toc08 100ms/div v out1 0v 0v 0v v out2 5v/div 0 en v rst out-of-phase waveform max1875 toc09 1 s/div v out1 20mv/div v out2 20mv/div 12v v lx1 v lx2 0v 0v 12v max1875/max1876 dual 180 out-of-phase pwm step- down controllers with por _______________________________________________________________________________________ 5 externally synchronized switching waveform max1875 toc10 400ns/div v out1 10mv/div ac-coupled 5v 5v 0v 0v v sync v ck0 v lx1 10v 0v cko output waveform max1875 toc11 400ns/div v out1 10mv/div ac-coupled 5v 0v v ck0 v lx1 10v 0v sync = gnd cko output waveform max1875 toc12 400ns/div v out1 10mv/div 5v 0v v ck0 v lx1 10v 0v sync = v l typical operating characteristics (continued) (circuit of figure 1, v in = 12v, t a = +25 c, unless otherwise noted.) short-circuit current foldback and recovery max1875 toc13 4ms/div i out1 = 10a(5a/div) v out1 = 1.8v(1v/div) v out2 = 2.5v(1v/div) i out2 = 10a(5a/div) v out2 short
max1875/max1876 dual 180 out-of-phase pwm step- down controllers with por 6 _______________________________________________________________________________________ pin description pin name function 1 comp2 compensation pin for regulator 2 (reg2). compensate reg2 s control loop by connecting a series resistor (r comp2 ) and capacitor (c comp2a ) to gnd in parallel with a second compensation capacitor (c comp2b ) as shown in figure 1. 2 fb2 feedback input for regulator 2 (reg2). connect fb2 to a resistive-divider between reg2 s output and gnd to adjust the output voltage between 1v and 18v. to set the output voltage below 1v, connect fb2 to a resistive voltage-divider from ref to reg2 s output. see the setting the output voltage section. 3 ilim2 current-limit adjustment for regulator 2 (reg2). the pgnd lx2 current-limit threshold defaults to 100mv if ilim2 is connected to v l . connect a resistor (r ilim2 ) from ilim2 to gnd to adjust the reg2 s current-limit threshold (v ith2 ) from 50mv (r ilim2 = 100k ? ) to 300mv (r ilim2 = 600k ? ). see the setting the valley current limit section. 4 osc oscillator frequency set input. the controller generates the clock signal by dividing down the oscillator, so the switching frequency equals half the synchronization frequency (f sw = f osc /2). connect a resistor from osc to gnd (r osc ) to set the switching frequency from 100khz (r osc = 60k ? ) to 600khz (r osc = 10k ? ). the controller still requires r osc when an external clock is connected to sync. when using sync, set r osc for one half of the sync input. 5 v+ input supply voltage. 4.75v to 23v. 6 ref 2v reference output. bypass to gnd with a 0.22f or greater ceramic capacitor. 7 gnd analog ground 8 cko clock output. clock output for external 2- or 4-phase synchronization (see the clock synchronization (sync, cko) section). 9 sync synchronization input or clock output selection input. sync has three operating modes. connect sync to a 200khz to 1200khz clock for external synchronization. connect sync to gnd for 2-phase operation as a master controller. connect sync to v l for 4-phase operation as a master controller (see the clock synchronization (sync, cko) section). 10 ilim1 current-limit adjustment for regulator 1 (reg1). the pgnd lx1 current-limit threshold defaults to 100mv if ilim1 is connected to v l . connect a resistor (r ilim1 ) from ilim1 to gnd to adjust reg1 s current-limit threshold (v ith1 ) from 50mv (r ilim1 = 100k ? ) to 300mv (r ilim1 = 600k ? ). see the setting the valley current limit section. 11 fb1 feedback input for regulator 1 (reg1). connect fb1 to a resistive-divider between reg1 s output and gnd to adjust the output voltage between 1v and 18v. to set the output voltage below 1v, connect fb1 to a resistive voltage-divider from ref and reg1 s output. see the setting the output voltage section. 12 comp1 compensation pin for regulator 1 (reg1). compensate reg1 s control loop by connecting a series resistor (r comp1 ) and capacitor (c comp1a ) to gnd in parallel with a second compensation capacitor (c comp1b ) as shown in figure 1. 13 rst open-drain reset output (max1876 only). rst is low when either output voltage is more than 10% below its regulation point. after soft-start is completed and both outputs exceed 90% of their nominal output voltage (v fb _ > 0.9v), rst becomes high impedance after a 140ms delay and remains high impedance as long as both outputs maintain regulation. connect a resistor between rst and the logic supply for logic-level voltages.
detailed description dc-dc pwm controller the max1875/max1876 step-down converters use a pwm voltage-mode control scheme (figure 2) for each out-of-phase controller. the controller generates the clock signal by dividing down the internal oscillator or sync input when driven by an external clock, so each controller s switching frequency equals half the oscillator frequency (f sw = f osc /2). an internal transconductance error amplifier produces an integrated error voltage at the comp pin, providing high dc accuracy. the voltage at comp sets the duty cycle using a pwm comparator and a ramp generator. at each rising edge of the clock, reg1 s high-side n-channel mosfet turns on and remains on until either the appropriate duty cycle or until the maximum duty cycle is reached. reg2 operates out- of-phase, so the second high-side mosfet turns on at each falling edge of the clock. during each high-side mosfet s on-time, the associated inductor current ramps up. during the second-half of the switching cycle, the high- side mosfet turns off and the low-side n-channel mosfet turns on. now the inductor releases the stored energy as its current ramps down, providing current to the output. under overload conditions, when the induc- tor current exceeds the selected valley current-limit (see the current-limit circuit (ilim_) section), the high-side mosfet does not turn on at the appropriate clock edge and the low-side mosfet remains on to let the inductor current ramp down. synchronized out-of-phase operation the two independent regulators in the max1875/ max1876 operate 180 out-of-phase to reduce input fil- tering requirements, reduce electromagnetic interference (emi), and improve efficiency. this effectively lowers component cost and saves board space, making the max1875/max1876 ideal for cost-sensitive applications. dual-switching regulators typically operate both controllers in-phase, and turn on both high-side mosfets at the same time. the input capacitor must then support the instantaneous current requirements of both controllers simultaneously, resulting in increased ripple voltage and current when compared to a single switching regulator. the higher rms ripple current lowers efficiency due to power loss associated with the input capacitor s effective series resistance (esr). this typically requires more low-esr input capacitors in parallel to minimize input voltage ripple and esr-related losses, or to meet the necessary ripple-current rating. max1875/max1876 dual 180 out-of-phase pwm step- down controllers with por _______________________________________________________________________________________ 7 pin description (continued) pin name function 14 dh1 high-side gate driver output for regulator 1 (reg1). dh1 swings from lx1 to bst1. 15 lx1 external inductor connection for regulator 1 (reg1). connect lx1 to the switched side of the inductor. lx1 serves as the lower supply rail for the dh1 high-side gate driver. 16 bst1 boost flying-capacitor connection for regulator 1 (reg1). connect bst1 to an external ceramic capacitor and diode according to figure 1. 17 dl1 low-side gate-driver output for regulator 1 (reg1). dl1 swings from pgnd to v l . 18 pgnd power ground 19 v l internal 5v linear-regulator output. supplies the regulators and powers the low-side gate drivers and external boost circuitry for the high-side gate drivers. 20 dl2 low-side gate-driver output for regulator 2 (reg2). dl2 swings from pgnd to v l . 21 bst2 boost flying-capacitor connection for regulator 2 (reg2). connect bst2 to an external ceramic capacitor and diode according to figure 1. 22 lx2 external inductor connection for regulator 2 (reg2). connect lx2 to the switched side of the inductor. lx2 serves as the lower supply rail for the dh2 high-side gate driver. 23 dh2 high-side gate-driver output for regulator 2 (reg2). dh2 swings from lx2 to bst2. 24 en active-high enable input. a logic low shuts down both controllers. connect to v l for always-on operation.
max1875/max1876 with dual synchronized out-of-phase operation, the max1875/max1876 s high-side mosfets turn-on 180 out-of-phase. the instantaneous input current peaks of both regulators no longer overlap, resulting in reduced rms ripple current and input voltage ripple. this reduces the required input capacitor ripple-current rating, allow- ing fewer or less expensive capacitors, and reduces shielding requirements for emi. the out-of-phase waveforms in the typical operating characteristics demonstrate synchronized 180 out-of-phase operation. internal 5v linear regulator (v l ) all max1875/max1876 functions are internally powered from an on-chip, low-dropout 5v regulator. the maxi- mum regulator input voltage (v+) is 23v. bypass the regulator s output (v l ) with a 4.7f ceramic capacitor to pgnd. the v l dropout voltage is typically 500mv, so when v+ is greater than 5.5v, v l is typically 5v. the max1875/max1876 also employs an undervoltage lockout circuit that disables both regulators when v l falls below 4.5v. v l should also be bypassed to gnd with a 0.1f capacitor. dual 180 out-of-phase pwm step- down controllers with por 8 _______________________________________________________________________________________ v+ bst1 dh1 lx1 dl1 v l bst2 dh2 lx2 dl2 fb1 comp1 *irf7811w **optional fb2 comp2 pgnd ref gnd osc sync cko ilim1 ilim2 en off on reset output clock output v l rst (max 1876 only) max1875 max1876 c v+ 0.22 f c in1 2 10 f c out1 4 220 f n h1* n l1* l1 1 h output1 v out = 1.8v v in 6v - 23v c bst1 0.1 f r1a 8.06k ? r1b 10k ? r comp1 5.9k ? c comp1a 10nf c comp1b 100pf c ref 0.22 f c comp2a 6.8nf c comp2b 100pf r comp2 8.2k ? r2b 10k ? 96.5k ? 140k ? r2a 15k ? 4.7 ? 4.7 ? r v+ 4.7 ? n l2* ** ** n h2* l2 1.2 h c out2 4 220 f c in2 2 10 f output2 v out = 2.5v c bst2 0.1 f c vl 4.7 f 0.1 f 118k ? d3 cmssh-3 84.5k ? d2 cmssh-3 figure 1. standard application circuit
the internal v l linear regulator can source over 50ma to supply the ic, power the low-side gate driver, charge the external boost capacitor, and supply small external loads. when driving large fets, little or no regulator cur- rent may be available for external loads. for example, when switched at 600khz, a single large fet with 18nc total gate charge requires 18nc ? 600khz = 11ma. to drive larger mosfets, or deliver larger loads, connect v l to an external power supply from 4.75v to 5.5v. max1875/max1876 dual 180 out-of-phase pwm step- down controllers with por _______________________________________________________________________________________ 9 converter #1 r s q ilim1 dl1 pgnd lx1 dh1 bst1 v l - 0.5v fb1 comp1 soft-start dac oscillator osc sync ck0 v+ 5v linear regulator v l gnd ref dl2 lx2 dh2 bst2 ilim2 fb2 comp2 converter 2 reset en uvlo and shutdown v ref 2.0v max1875 max1876 rst (max1876 only) v ref v l q 5 a figure 2. functional diagram
max1875/max1876 high-side gate-drive supply (bst_) gate-drive voltages for the high-side n-channel switch- es are generated by the flying-capacitor boost circuits (figure 3). a boost capacitor (connected from bst_ to lx_) provides power to the high-side mosfet driver. on startup, the synchronous rectifier (low-side mosfet) forces lx_ to ground and charges the boost capacitor to 5v. on the second half-cycle, after the low-side mosfet turns off, the high-side mosfet is turned on by closing an internal switch between bst_ and dh_. this provides the necessary gate-to-source voltage to turn on the high- side switch, an action that boosts the 5v gate-drive signal above v in . the current required to drive the high- side mosfet gates (f switch ? q g ) is ultimately drawn from v l . mosfet gate drivers (dh_, dl_) the dh and dl drivers are optimized for driving moder- ate-size n-channel high-side and larger low-side power mosfets. this is consistent with the low-duty factor seen with large v in - v out differential. the dl_ low-side drive waveform is always the complement of the dh_ high-side drive waveform (with controlled dead time to prevent cross-conduction or shoot-through ). an adap- tive dead-time circuit monitors the dl_ output and pre- vents the high-side fet from turning on until dl_ is fully off. there must be a low-resistance, low-inductance path from the dl_ driver to the mosfet gate in order for the adaptive dead-time circuit to work properly. otherwise, the sense circuitry in the max1875/max1876 interprets the mosfet gate as off while there is actu- ally charge still left on the gate. use very short, wide traces (50mils to 100mils wide if the mosfet is 1in from the device). the dead time at the dh-off edge is deter- mined by a fixed 30ns internal delay. synchronous rectification reduces conduction losses in the rectifier by replacing the normal low-side schottky catch diode with a low-resistance mosfet switch. additionally, the max1875/max1876 uses the synchro- nous rectifier to ensure proper startup of the boost gate- driver circuit and to provide the current-limit signal. the internal pulldown transistor that drives dl_ low is robust, with a 0.5 ? (typ) on-resistance. this low on- resistance helps prevent dl_ from being pulled up dur- ing the fast rise-time of the lx_ node, due to capacitive coupling from the drain to the gate of the low-side syn- chronous-rectifier mosfet. however, for high-current applications, some combinations of high- and low-side fets can cause excessive gate-drain coupling, leading to poor efficiency, emi, and shoot-through currents. this can be remedied by adding a resistor (typically less than 5 ? ) in series with bst_, which increases the turn-on time of the high-side fet without degrading the turn-off time (figure 3). current-limit circuit (ilim_) the current-limit circuit employs a valley current-sens- ing algorithm that uses the on-resistance of the low-side mosfet as a current-sensing element. if the current- sense signal is above the current-limit threshold, the max1875/max1876 does not initiate a new cycle (figure 4). since valley current sensing is employed, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple cur- rent. therefore, the exact current-limit characteristic and maximum load capability are a function of the low-side mosfet s on-resistance, current-limit threshold, induc- tor value, and input voltage. the reward for this uncer- tainty is robust, lossless overcurrent sensing that does not require costly sense resistors. the adjustable current limit accommodates mosfets with a wide range of on-resistance characteristics (see the design procedure section). the current-limit thresh- old is adjusted with an external resistor at ilim_ (figure 1). the adjustment range is from 50mv to 300mv, cor- responding to resistor values of 100k ? to 600k ? . in adjustable mode, the current-limit threshold across the low-side mosfet is precisely 1/10th the voltage seen at ilim_. however, the current-limit threshold defaults to 100mv when ilim is tied to v l . the logic threshold for switchover to this 100mv default value is approxi- mately v l - 0.5v. adjustable foldback current limit reduces power dissi- pation during short-circuit conditions (see the design procedure section). carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the cur- rent-sense signals seen by lx_ and pgnd. the ic must be mounted close to the low-side mosfet with short, direct traces making a kelvin sense connection so that trace resistance does not add to the intended sense resistance of the low-side mosfet. undervoltage lockout and startup if v l drops below 4.5v, the max1875/max1876 assumes that the supply and reference voltages are too low to make valid decisions and activates the undervoltage lock- out (uvlo) circuitry which forces dl and dh low to inhibit switching. rst is also forced low during uvlo. after v l rises above 4.5v, the controller powers up the outputs. enable (en), soft-start, and soft-stop pull en high to enable or low to shutdown both regula- tors. during shutdown the supply current drops to 1ma (max), lx enters a high-impedance state (dh_ con- nected to lx_, and dl_ connected to pgnd), and comp_ is discharged to gnd through a 17 ? resistor. v l and ref remain active in shutdown. for always-on operation, connect en to v l . dual 180 out-of-phase pwm step- down controllers with por 10 ______________________________________________________________________________________
on the rising edge of en both controllers enter soft- start. soft-start gradually ramps up to the reference voltage seen by the error amplifier in order to control the outputs rate of rise and reduce input surge cur- rents during startup. the soft-start period is 1024 clock cycles (1024/f sw ), and the internal soft-start dac ramps up the voltage in 64 steps. the output reaches regulation when soft-start is completed. on the falling edge of en both controllers simultaneously enter soft- stop, which reverses the soft-start ramp. the part enters shutdown after soft-stop is complete. reset output (max1876 only) rst is an open-drain output. rst pulls low when either output falls below 90% of its nominal regulation voltage. once both outputs exceed 90% of their nominal regulation voltages and both soft-start cycles are completed, rst goes high impedance. to obtain a logic-voltage output, connect a pullup resistor from rst to the logic supply volt- age. a 100k ? resistor works well for most applications. if unused, leave rst grounded or unconnected. clock synchronization (sync, cko) sync serves two functions: sync selects the clock output (cko) type used to synchronize slave con- trollers, or it serves as a clock input so the max1875/max1876 can be synchronized with an exter- nal clock signal. this allows the max1875/max1876 to funtion as either a master or slave. cko provides a clock signal synchronized to the max1875/max1876s switching frequency, allowing either in-phase (sync = gnd) or 90 out-of-phase (sync = v l ) synchronization of additional dc-dc controllers (figure 5). the max1875/max1876 support the following three operat- ing modes: sync = gnd: the cko output frequency equals reg1 s switching frequency (f cko = f dh1 ) and the cko signal is in phase with reg1 s switching fre- quency. this provides 2-phase operation when syn- chronized with a second slave controller. sync = vl: the cko output frequency equals two times reg1 s switching frequency (f cko = 2f dh1 ) and the cko signal is phase shifted by 90 with respect to reg1 s switching frequency. this pro- vides 4-phase operation when synchronized with a second max1875/max1876 (slave controller). sync driven by external oscillator: the controller generates the clock signal by dividing down the sync input signal, so that the switching frequency equals half the synchronization frequency (f sw = f sync /2). reg1 s conversion cycles initiate on the ris- ing edge of the internal clock signal. the cko output frequency and phase match reg1 s switching fre- quency (f cko = f dh1 ) and the cko signal is in phase. note that the max1875/max1876 still require r osc when sync is externally clocked and the inter- nal oscillator frequency should be set to 50% of the synchronization frequency (f osc = 0.5 f sync ). thermal overload protection thermal overload protection limits total power dissipation in the max1875/max1876. when the device s die-junc- tion temperature exceeds t j = +160 c, an on-chip ther- mal sensor shuts down the device, forcing dl_ and dh_ low, allowing the ic to cool. the thermal sensor turns the part on again after the junction temperature cools by 10 c. during thermal shutdown, the regulators shut down, rst goes low, and soft-start is reset. if the v l lin- ear-regulator output is short-circuited, thermal-overload protection is triggered. design procedure effective input voltage range although, the max1875/max1876 controllers can oper- ate from input supplies ranging from 4.75v to 23v, the input voltage range can be effectively limited by the max1875/max1876s duty-cycle limitations. the maxi- mum input voltage is limited by the minimum on-time (t on(min) ): v v tf in max out on min sw () () max1875/max1876 dual 180 out-of-phase pwm step- down controllers with por ______________________________________________________________________________________ 11 v l bst_ dh_ lx_ 5 ? input (v in ) max1875 figure 3. reducing the switching-node rise time
max1875/max1876 where t on(min) is 100ns. the minimum input voltage is limited by the switching frequency and minimum off- time, which determine the maximum duty cycle (d max = 1 - f sw t off(min) ): where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances. v drop2 is the sum of the resistances in the charging path, includ- ing high-side switch, inductor, and pc board resis- tances. setting the output voltage for 1v or greater output voltages, set the max1875/ max1876 output voltage by connecting a voltage- divider from the output to fb_ to gnd (figure 6). select r_b (fb_ to gnd resistor) to between 1k ? and 10k ? . calculate r_a (out_ to fb_ resistor) with the following equation: where v set = 1v (see the electrical characteristics ) and v out can range from v set to 18v. for output voltages below 1v, set the max1875/ max1876 output voltage by connecting a voltage- divider from the output to fb_ to ref (figure 6). select r_c (fb to ref resistor) in the 1k ? to 10k ? range. calculate r_a with the following equation: where v set = 1v, v ref = 2v (see the electrical characteristics ), and v out can range from 0 to v set . ra rc vv vv set out ref set __ = ? ? ? ? ? ? - - ra rb v v out set __ = ? ? ? ? ? ? ? ? ? ? ? ? ? ? -1 v vv ft vv in min out drop sw off min drop drop () () = + ? ? ? ? ? ? ? ? + 1 21 1- - dual 180 out-of-phase pwm step- down controllers with por 12 ______________________________________________________________________________________ inductor current i limit i load 0 time -i peak figure 4. valley current-limit threshold point sync slave osc sync ck0 master v l 4-phase system 2-phase system dh1 dh2 dh1 dh2 master slave 180 phase shift 90 phase shift dh1 dh2 dh1 dh2 master slave max1875 sync slave osc osc sync ck0 master v l max1875 max1875 figure 5. synchronized controllers
setting the switching frequency the controller generates the clock signal by dividing down the internal oscillator or sync input signal when driven by an external oscillator, so the switching frequen- cy equals half the oscillator frequency (f sw = f osc /2). the internal oscillator frequency is set by a resistor (r osc ) connected from osc to gnd. the relationship between f sw and r osc is: where f sw is in hz, f osc is in hz, and r osc is in ? . for example, a 600khz switching frequency is set with r osc = 10k ? . higher frequencies allow designs with lower inductor values and less output capacitance. consequently, peak currents and i 2 r losses are lower at higher switching frequencies, but core losses, gate- charge currents, and switching losses increase. a rising clock edge on sync is interpreted as a syn- chronization input. if the sync signal is lost, the inter- nal oscillator takes control of the switching rate, returning the switching frequency to that set by r osc . this maintains output regulation even with intermittent sync signals. when an external synchronization signal is used, r osc should set the switching frequency to one half sync rate (f sync ). inductor selection three key inductor parameters must be specified for operation with the max1875/max1876: inductance value (l), peak-inductor current (i peak ), and dc resis- tance (r dc ). the following equation assumes a constant ratio of inductor peak-to-peak ac current to dc average current (lir). for lir values too high, the rms currents are high, and therefore i 2 r losses are high. large induc- tances must be used to achieve very low lir values. typically inductance is proportional to resistance (for a given package type) which again makes i 2 r losses high for very low lir values. a good compromise between size and loss is a 30% peak-to-peak ripple current to average-current ratio (lir = 0.3). the switching frequen- cy, input voltage, output voltage, and selected lir determine the inductor value as follows: where v in , v out , and i out are typical values (so that efficiency is optimum for typical conditions). the switch- ing frequency is set by r osc (see the setting the switching frequency section). the exact inductor value is not critical and can be adjusted in order to make trade-offs among size, cost, and efficiency. lower inductor values minimize size and cost, but also improve transient response and reduce efficiency due to higher peak currents. on the other hand, higher inductance increases efficiency by reducing the rms current. however, resistive losses due to extra wire turns can exceed the benefit gained from lower ac current levels, especially when the inductance is increased without also allowing larger inductor dimensions. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. the inductor s saturation rating must exceed the peak- inductor current at the maximum defined load current (i load(max) ): setting the valley current limit the minimum current-limit threshold must be high enough to support the maximum expected load current with the worst-case low-side mosfet on-resistance value since the low-side mosfet s on-resistance is used as the current-sense element. the inductor s valley current occurs at i load(max) minus half of the ripple current. the current-sense threshold voltage (v ith ) should be greater than voltage on the low-side mosfet during the ripple-current valley: where r ds(on) is the on-resistance of the low-side mosfet (n l ). use the maximum value for r ds(on) from the low-side mosfet s data sheet, and additional margin to account for r ds(on) rise with temperature is also recommended. a good general rule is to allow 0.5% additional resistance for each c of the mosfet junction temperature rise. connect ilim_ to vl for the default 100mv (typ) cur- rent-limit threshold. for an adjustable threshold, con- nect a resistor (r ilim _) from ilim_ to gnd. the relationship between the current-limit threshold (v ith _) and r ilim _ is: where r ilim _ is in ? and v ith _ is in v. r v a ilim ith _ _ . = 05 vr i lir ith ds onmax load max > ? ? ? ? ? ? (, ) ( ) 1 2 - ii lir i peak load max load max =+ ? ? ? ? ? ? () () 2 l vvv v f i lir out in out in sw out = () - r hz s f osc sw = 610 9 ? - max1875/max1876 dual 180 out-of-phase pwm step- down controllers with por ______________________________________________________________________________________ 13
max1875/max1876 an r ilim resistance range of 100k ? to 600k ? corre- sponds to a current-limit threshold of 50mv to 300mv. when adjusting the current limit, 1% tolerance resistors minimize error in the current-limit threshold. for foldback current limit, a resistor (r fbi ) is added from ilim pin to output. the value of r ilim and r fbi can then be calculated as follows: first select the percentage of foldback, p fb , from 15% to 30%, then: input capacitor the input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit s switching. the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents as defined by the following equation: i rms has a maximum value when the input voltage equals twice the output voltage (v in = 2v out ), so i rms(max) = i load / 2. for most applications, non- tantalum capacitors (ceramic, aluminum, polymer, or os-con) are preferred at the input due to their robust- ness with high inrush currents typical of systems that can be powered from very low impedance sources. additionally, two (or more) smaller-value low-esr capac- itors can be connected in parallel for lower cost. choose an input capacitor that exhibits less than +10 c temper- ature rise at the rms input current for optimal long-term reliability. output capacitor the key selection parameters for the output capacitor are capacitance value, esr, and voltage rating. these parameters affect the overall stability, output ripple volt- age, and transient response. the output ripple has two components: variations in the charge stored in the out- put capacitor, and the voltage drop across the capaci- tor s esr caused by the current flowing into and out of the capacitor: the output voltage ripple as a consequence of the esr and output capacitance is: where i p-p is the peak-to-peak inductor current (see the inductor selection section). these equations are suit- able for initial capacitor selection, but final values should be verified by testing in a prototype or evaluation circuit. vir v i cf i vv fl v v ripple esr p p esr ripple c pp out sw pp in out sw out in () () = = = ? ? ? ? ? ? ? ? ? ? ? ? - - - - 8 vv v ripple ripple esr ripple c ?+ () () ii vvv v rms load out in out in = () - r pv p and r vpr vvp fbi fb out fb ilim ith fb fbi out ith fb = = [] 510 1 10 1 10 1 6 - - - -- () () () dual 180 out-of-phase pwm step- down controllers with por 14 ______________________________________________________________________________________ max1875 out_ r_a r_b fb_ v out_ > 1v max1875 out_ r_c r_a fb_ ref v out_ < 1v figure 6. adjustable output voltage
as a general rule, a smaller inductor ripple current results in less output ripple voltage. since inductor ripple current depends on the inductor value and input voltage, the out- put ripple voltage decreases with larger inductance and increases with higher input voltages. however, the induc- tor ripple current also impacts transient-response perfor- mance, especially at low v in - v out differentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capac- itors by a sudden load step. the amount of output-volt- age sag is also a function of the maximum duty factor, which can be calculated from the minimum off-time and switching frequency: where t off(min) is the minimum off-time (see the electrical characteristics ), and f sw is set by r osc (see the setting the switching frequency section). compensation each voltage-mode controller section employs a transconductance error amplifier whose output is the compensation point of the control loop. the control loop is shown in figure 7. for frequencies much lower than nyquist, the pwm block can be simplified to a voltage amplifier. connect r comp_ and c comp_a from comp to gnd to compensate the loop (see figure 7). the inductor, output capacitor, compensation resistor, and compensation capacitors determine the loop stability. since the inductor and output capacitor are chosen based on performance, size, and cost, select the com- pensation resistor and capacitors to optimize control- loop stability. to determine the loop gain (a l ), consider the gain from fb to comp (a comp/fb ), from comp to lx (a lx/comp ), and from lx to fb (a fb/lx ). the total loop gain is: where: assuming an ideal integrator, and assuming that c comp_b is much less than c comp_a . for frequencies lower than nyquist. therefore: for an ideal integrator this loop gain approaches infinity at dc. in reality the g m amplifier has a finite output impedance which imposes a finite, but large, loop gain. it is this large loop gain that provides dc load accura- cy. the dominant pole occurs due to the integrator, and for this analysis, it can be approximated to occur at dc. r comp creates a zero at: the inductor and capacitor form a double pole at: at some higher frequency the output capacitor s impedance becomes insignificant compared to its esr, and the lc system becomes more like an lr system, turning a double pole into a single pole. this zero occurs at: f rc esr esr out = 1 2 f lc lc out = 1 2 f rc z comp a comp comp a __ __ = 1 2 a g sc sr c sr c v v v v sr c slc l m comp comp a comp comp a comp comp b in ramp set out esr out out ? + + + + _ _ _ _ 1 1 1 1 2 a v v v v sr c slc sr c v v sr c vslc fb lx fb lx set out esr out out esr out set out esr out out out / == + ++ ? + + 1 1 1 1 2 2 a v v v v lx comp lx comp in ramp / == a v v g sc sr c sr c comp fb comp fb m comp comp comp comp a comp comp b / _ _ _ =? + + 1 1 aaaa l comp fb lx comp fb lx = // / v li i v vf t cv vv vf t sag load load out in sw off min out out in out in sw off min = ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () () () 12 2 2 - - - max1875/max1876 dual 180 out-of-phase pwm step- down controllers with por ______________________________________________________________________________________ 15
max1875/max1876 a final pole is added using c comp_b to reduce the gain and attenuate noise after crossover. this pole (f comp_b ) occurs at: figure 8 shows a bode plot of the poles and zeros in their relative locations. near crossover the following approximations can be made to simplify the loop-gain equation: r comp has much higher impedance than c comp . this is true if, and only if, crossover occurs above f z_comp_a . if this is true, c comp_a can be ignored (as a short to ground). r esr is much higher impedance than c out . this is true if, and only if, crossover occurs well after the out- put capacitor s esr zero. if this is true, c out becomes an insignificant part of the loop gain and can be ignored (as a short to ground). c comp_b is much higher impedance than r comp and can be ignored (as an open circuit). this is true if, and only if, crossover occurs far below f comp_b . the following loop gain equation can be found by using these previous approximations with figure 7: setting the loop gain to 1 and solving for the crossover frequency yields: to ensure stability, select r comp to meet the following criteria: unity-gain crossover must occur below 1/5th of the switching frequency. for reasonable phase margin using type 1 compen- sation, f co must be larger than 5 ? f esr . choose c comp_a so that f z_comp_a equals half f lc using the following equation: choose c comp_b so that f comp_b occur at 3 times f co using the following equation: mosfet selection the max1875/max1876s step-down controller drives two external logic-level n-channel mosfets as the cir- cuit switch elements. the key selection parameters are: on-resistance (r ds(on) ) maximum drain-to-source voltage (v ds(max) ) c fr comp b co comp _ = () 1 23 c lc r comp a out comp _ = 2 f gbw v v v v grr l co in ramp set out m comp comp esr == _ 2 a v v v v grr sl l in ramp set out m comp comp esr ? _ f rc comp b comp comp b _ _ = 1 2 dual 180 out-of-phase pwm step- down controllers with por 16 ______________________________________________________________________________________ comp_ r comp_ c comp_a c comp_b g m_group p w m v c v set dh dl n n l lx fb v out r esr c out comp_ r comp_ c comp_a c comp_b g m_group v set l lx fb r esr c out gain = +v in /v ramp for frequencies lower than nyquist = figure 7. fixed-frequency voltage-mode control loop
minimum threshold voltage (v th(min) ) total gate charge (q g ) reverse transfer capacitance (c rss ) power dissipation all four n-channel mosfets must be a logic-level type with guaranteed on-resistance specifications at v gs 4.5v. for maximum efficiency, choose a high-side mosfet (n h _) that has conduction losses equal to the switching losses at the optimum input voltage. check to ensure that the conduction losses at minimum input voltage do not exceed mosfet package thermal limits, or violate the overall thermal budget. also, check to ensure that the conduction losses plus switching losses at the maximum input voltage do not exceed package ratings or violate the overall thermal budget. ensure that the max1875/max1876 dl_ gate drivers can drive n l _. in particular, check that the dv/dt caused by n h _ turning on does not pull up the n l _ gate through n l _ s drain-to-gate capacitance. this is the most frequent cause of cross-conduction problems. gate-charge losses are dissipated by the driver and do not heat the mosfet. all mosfets must be selected so that their total gate charge is low enough that v l can power all four drivers without overheating the ic: mosfet package power dissipation often becomes a dominant design factor. i 2 r power losses are the great- est heat contributor for both high-side and low-side mosfets. i 2 r losses are distributed between n h _ and n l _ according to duty factor as shown in the equations below. switching losses affect only the high-side mosfet, since the low-side mosfet is a zero-voltage switched device when used in the buck topology. calculate mosfet temperature rise according to pack- age thermal-resistance specifications to ensure that both mosfets are within their maximum junction tem- perature at high ambient temperature. the worst-case dissipation for the high-side mosfet (p nh ) occurs at both extremes of input voltage, and the worst-case dis- sipation for the low-side mosfet (p nl ) occurs at maxi- mum input voltage. i gate is the average dh driver output current capability determined by: where r ds(on)dh is the high-side mosfet driver s on- resistance (5 ? max), and r gate is any series resis- tance between dh and bst (figure 3). where p nh(conduction) is the conduction power loss in the high-side mosfet, and p nl is the total low-side power loss. to reduce emi caused by switching noise, add a 0.1f ceramic capacitor from the high-side switch drain to the low-side switch source or add resistors in series with dl_ and dh_ to increase the mosfets turn-on and turn-off times. applications information dropout performance when working with low input voltages, the output-volt- age adjustable range for continuous-conduction opera- tion is restricted by the minimum off-time (t off(min) ). for best dropout performance, use the lowest (100khz) switching-frequency setting. manufacturing tolerances and internal propagation delays introduce an error to pir v v pp p pi r v v nh conduction load ds on nh out in nh total nh switching nh conduction nl load ds on nl out in ()() ()( )( ) () = ? ? ? ? ? ? =+ = ? ? ? ? ? ? ? ? ? ? ? ? 2 2 1- i v rr gate l ds on dh gate = + () 2 () p vi f q q i nh switching in load osc gs gd gate () = + ? ? ? ? ? ? 2 pvq f vl in g total sw = _ max1875/max1876 dual 180 out-of-phase pwm step- down controllers with por ______________________________________________________________________________________ 17 bode plot for voltage- mode controllers frequency (mhz) gain (db) 0.1 0.01 -40 -30 -20 -10 0 10 20 30 40 50 0.001 1 f z-comp_a f comp_b f lc f co f esr f switch figure 8. voltage-mode loop analysis
max1875/max1876 the switching frequency and minimum off-time specifi- cations. this error is more significant at higher frequen- cies. also, keep in mind that transient response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the v sag equation in the design procedure section). the absolute point of dropout is when the inductor cur- rent ramps down during the minimum off-time ( ? i down ) as much as it ramps up during the maximum on-time ( ? i up ). the ratio h = ? i up / ? i down is an indicator of the ability to slew the inductor current higher in response to increased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and v sag greatly increases unless additional output capacitance is used. a reasonable minimum value for h is 1.5, but adjusting this up or down allows tradeoffs between v sag , output capacitance, and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; v drop2 is the sum of the resistances in the charging path, includ- ing high-side switch, inductor, and pc board resis- tances; and t off(min) is from the electrical characteristics . the absolute minimum input voltage is calculated with h = 1. if the calculated v+ (min) is greater than the required minimum input voltage, then reduce the operating fre- quency or add output capacitance to obtain an accept- able v sag . if operation near dropout is anticipated, calculate v sag to be sure of adequate transient response. dropout design example: v out = 5v f sw = 600khz t off(min) = 250ns v drop1 = v drop2 = 100mv h = 1.5 calculating again with h = 1 gives the absolute limit of dropout: therefore, v in must be greater than 6v, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 6.58v. improving noise immunity applications where the max1875/max1876 must oper- ate in noisy environments can typically adjust their con- troller s compensation to improve the system s noise immunity. in particular, high-frequency noise coupled into the feedback loop causes jittery duty cycles. one solution is to lower the crossover frequency (see the compensation section). pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. this is especially true for dual converters where one channel can affect the other. refer to the max1875/max1876 ev kit data sheet for a specific layout example. if possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. follow these guidelines for good pc board layout: isolate the power components on the top side from the analog components on the bottom side with a ground shield. use a separate pgnd plane under the out1 and out2 sides (referred to as pgnd1 and pgnd2). avoid the introduction of ac currents into the pgnd1 and pgnd2 ground planes. run the power plane ground currents on the top side only. use a star ground connection on the power plane to minimize the crosstalk between out1 and out2. keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. connect gnd and pgnd together close to the ic. do not connect them together anywhere else. carefully follow the grounding instructions under step 4 of the layout procedure section. v vmv khz ns mv mv v in min () ()() = + ? ? ? ? ? ? += ? 5 100 1 600 250 100 100 6 - v vmv khz ns mv mv v in min () . ( )( ) . = + ? ? ? ? ? ? += ? 5 100 1 1 5 600 250 100 100 6 58 - v vv hf t vv in min out drop sw off min drop drop () () = + ? ? ? ? ? ? ? ? + 1 21 1- - dual 180 out-of-phase pwm step- down controllers with por 18 ______________________________________________________________________________________
keep the power traces and load connections short. this practice is essential for high efficiency. use thick copper pc boards (2oz vs. 1oz) to enhance full-load efficiency by 1% or more. lx_ and pgnd connections to the synchronous rec- tifiers for current limiting must be made using kelvin sense connections to guarantee the current-limit accuracy. with 8-pin so mosfets, this is best done by routing power to the mosfets from outside using the top copper layer, while connecting pgnd and lx_ underneath the 8-pin so package. when trade-offs in trace lengths must be made, allow the inductor-charging path to be made longer than the discharge path. since the average input current is lower than the average output current in step-down converters, this minimizes the power dis- sipation and voltage drops caused by board resis- tance. for example, allow some extra distance between the input capacitors and the high-side mosfet rather than to allow distance between the inductor and the low-side mosfet or between the inductor and the output filter capacitor. ensure that the feedback connection to c out_ is short and direct. route high-speed switching nodes (bst_, lx_, dh_, and dl_) away from the sensitive analog areas (ref, comp_, ilim_, and fb_). use pgnd1 and pgnd2 as emi shields to keep radiated noise away from the ic, feedback dividers, and analog bypass capacitors. make all pin-strap control input connections (ilim_, sync, and en) to analog ground (gnd) rather than power ground (pgnd). layout procedure 1) place the power components first, with ground termi- nals adjacent (n l _ source, c in _, and c out _). make all these connections on the top layer with wide, cop- per-filled areas (2oz copper recommended). 2) mount the controller ic adjacent to the synchronous rectifier mosfets (n l _), preferably on the back side in order to keep lx_, pgnd_, and dl_ traces short and wide. the dl_ gate trace must be short and wide, measuring 50mils to 100mils wide if the low-side mosfet is 1in from the controller ic. 3) group the gate-drive components (bst_ diodes and capacitors, and v l bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as follows: create a small analog ground plane near the ic. connect this plane to gnd and use this plane for the ground connection for the reference (ref) v+ bypass capacitor, compensation components, feed- back dividers, osc resistor, and ilim_ resistors (if any). connect gnd and pgnd together under the ic (this is the only connection between gnd and pgnd). 5) on the board s top side (power planes), make a star ground to minimize crosstalk between the two sides. chip information transistor count: 6688 process: bicmos max1875/max1876 dual 180 out-of-phase pwm step- down controllers with por ______________________________________________________________________________________ 19
max1875/max1876 dual 180 out-of-phase pwm step- down controllers with por 20 ______________________________________________________________________________________ v+ bst1 dh1 lx1 dl1 v l bst2 dh2 lx2 dl2 fb1 comp1 fb2 comp2 pgnd ref gnd osc sync ck0 ilim1 ilim2 en off on reset output clock output v l rst max1876 n l1 output1 = 1.8v, 10a n l2 n h2 output2 = 2.5v, 10a v in 4.75v to 23v typical operating circuit
max1875/max1876 dual 180 out-of-phase pwm step- down controllers with por maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 21 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qsop.eps

▲Up To Search▲

Price & Availability of MAX1875-MAX1876

	To Download MAX1875-MAX1876 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .